Device Scaling Considerations for Nanophotonic CMOS Global Interconnects,” Selected Topics in Quantum Electronics

Abstract—We introduce an analytical framework to understand the path for scaling nanophotonic interconnects to meet the energy and footprint requirements of CMOS global interconnects. We de-rive the device requirements for sub-100 fJ/cm/bit interconnects including tuning power, serialization–deserialization energy, and optical insertion losses. Using CMOS with integrated nanophoton-ics as an example platform, we derive the energy/bit, linear, and areal bandwidth density of optical interconnects. We also derive the targets for device performance which indicate the need for contin-ued improvements in insertion losses (<8 dB), laser efficiency, operational speeds (>40 Gb/s), tuning power (<100 μW/nm), serialization–deserialization (<10 fJ/bit/Operation), and necessity for spectrally selective devices with wavelength multiplexing (>6 channels). Index Terms—Coupled resonators, integrated optics devices, in-tegrated optoelectronic circuits, switching